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| SEMICONDUCTOR CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Description The Harris CD74HC123, CD74HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V. September 1997 Features * Overriding Reset Terminates Output Pulse * Triggering From the Leading or Trailing Edge * Q and Q Buffered Outputs * Separate Resets * Wide Range of Output-Pulse Widths * Schmitt Trigger on Both A and B Inputs * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH Ordering Information PART NUMBER CD74HC123E CD74HCT123E TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC PKG. NO. E16.3 E16.3 E16.3 E16.3 M16.15 M16.15 M16.15 M16.15 Pinout CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 (PDIP, SOIC) TOP VIEW 1A 1 1B 2 1R 3 1Q 4 2Q 5 2CX 6 2RXCX 7 GND 8 16 VCC 15 1RXCX 14 1CX 13 1Q 12 2Q 11 2R 10 2B 9 2A CD74HC423E CD74HCT423E CD74HC123M CD74HCT123M CD74HC423M CD74HCT423M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 1708.1 1 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Functional Diagram 1Cx 14 1Cx 1A 1 1B 2 1R 2R 2A 10 2B 2Cx 6 2Cx 2RxCx 7 2Rx VCC MONO 2 12 2Q 3 11 9 5 2Q MONO 1 4 1Q 15 1RxCx 13 1Q 1Rx VCC TRUTH TABLE INPUTS A CD74HC/HCT123 H X L X L CD74HC/HCT423 H X L X X L H X H H H H L L H L L H H X L H X H H H H H L L H L L H H B R Q OUTPUTS Q NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care. 2 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Thermal Information Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 3 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS VCC (V) -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 100 0.1 8 360 - 1 80 450 - 1 160 490 A A A NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT All UNIT LOADS 0.35 NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g. 360A max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER HC TYPES Minimum Input, Pulse Width A tWL 2 4.5 6 B tWH 2 4.5 6 100 20 17 100 20 17 125 25 21 125 25 21 150 30 26 150 30 26 ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS 4 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER R SYMBOL tWL VCC (V) 2 4.5 6 A and B Hold Time tH 2 4.5 6 Reset Removal Time tREM 2 4.5 6 Retrigger Time Number RX = 10K, CX = 0 Output Pulse Width Q or Q RX = 10K, CX = 10nF HCT TYPES Minimum Input, Pulse Width A B R A and B Hold Time Reset Removal Time Retrigger Time Number (Note 4) RX = 10K, CX = 0 Output Pulse Width Q or Q RX = 10K, CX = 10nF NOTE: 4. Time to trigger depends on the values of RX and CX. The output pulse width can only be extended when the time between the activegoing edges of the trigger input pulses meet the minimum retrigger time requirement. trT tW 5 5 40 50 50 38.7 63 51.3 38.2 76 51.8 ns s tWH tWL tH tREM 5 5 tWL 5 20 20 20 10 10 25 25 25 13 13 30 30 30 15 15 ns ns ns ns ns 40 50 38.7 51.3 38.2 51.8 s tW 5 trT 5 MIN 100 20 17 50 10 9 50 10 9 TYP 50 MAX -40oC TO 85oC MIN 125 25 21 65 13 11 65 13 11 TYP 63 MAX -55oC TO 125oC MIN 150 30 26 75 15 13 75 15 13 TYP 76 MAX 150 30 26 75 15 13 75 15 13 UNITS ns ns ns ns ns ns ns ns ns ns ns 5 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10K, CX = 0 25oC PARAMETER HC TYPES Trigger Propagation Delay A, B, R to Q tPHL CL = 50pF 2 4.5 CL = 15pF CL = 50pF A, B, R to Q tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Reset Propagation Delay R to Q or Q tPHL, tPLH CL = 50pF 5 6 2 4.5 6 Output Transition Time tTHL, tTLH CL = 50pF 2 4.5 6 Output Pulse Width RX = 10K, CX = 10pF Pulse Width Match Between Circuits In the Same Package RX = 10K, CX = 10pF Power Dissipation Capacitance Input Capacitance NOTES: 5. CPD is used to determine the dynamic power consumption, per multivibrator. 6. PD = (CPD + CX) VCC2 fi (CL VCC2 fO) where fi = input frequency, fO = Output Frequency, CL = Output Load Capacitance, I CX = External Capacitance VCC = Supply Voltage assuming fi -----tW CPD CIN CL = 15pF CL = 50pF 5 5 10 2 10 10 10 % pF pF 5 45 s 25 26 300 60 51 320 64 54 215 43 37 75 15 13 375 75 64 400 80 68 270 54 46 95 19 16 450 90 76 480 96 82 325 65 55 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 6 CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Test Circuits and Waveforms A A B = LOW A = HIGH B R tW Q tW tW VS tW VS Q tW tW B R VS tW VS B = LOW A = HIGH FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT (R) PULSE FOR 123 FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT (R) FOR 423 A B B A trT Q VS tW tW tW tW (R = HIGH) NOTE: Output pulse control using retrigger pulse for 123 and 423. FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD tW 8 6 4 2 103 8 6 4 2 102 8 6 4 2 10 0k 0.9 EXTERNAL CAPACITANCE (CX) = 10nF 0.8 0.7 "K" FACTOR 0.6 0.5 0.4 0.3 0.2 0.1 HCT EXTERNAL RESISTANCE (RX) = 10k TO 100k AMBIENT TEMPERATURE (TA) = 25oC OUTPUT PULSE WIDTH (s) RX = RX =1 0 k 101 8 6 4 2 103 2 DC SUPPLY VOLTAGE (VCC) = 5V AMBIENT TEMPERATURE (TA) = 25oC 4 68 2 4 68 2 4 68 2 105 104 106 EXTERNAL CAPACITANCE (CX) - pF 4 68 107 1 2 3 4 5 6 7 8 9 DC SUPPLY VOLTAGE (VCC) - VOLTS 10 11 FIGURE 4. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION OF CX FOR RX = 10k AND 100k FIGURE 5. TYPICAL "K" FACTOR AS A FUNCTION OF VCC 7 |
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